1. Field of the Invention
The present invention generally relates to high density integrated circuits and, more particularly, to regulating performance and conduction characteristics of MOSFET devices included therein.
2. Description of the Prior Art
The enhancements to performance and economy of manufacture derived from high density integration of semiconductor integrated circuits have been recognized for several years. During this same period of time, field effect transistor (FET) technology has generally become the technology of choice for all but the most critical of applications in view of scalability of field effect transistors to small sizes consistent with conduction requirements and other properties facilitating process economy, integration density and high manufacturing yield as well as exhibiting good operating margins and low drive current requirements. Field effect transistors function as switching device by using a field developed by a voltage on an insulated gate to control conduction in a channel under the gate in a body of semiconductor material.
It is well-recognized, however, that the conduction properties of semiconductor materials vary strongly with temperature while exhibiting some finite electrical resistance. Generally, bulk semiconductor resistance decreases with increase of temperature. Active devices must also be isolated from each other by insulator structures which generally surround the active devices and are poor conductors of heat. Even though very thin, the gate insulator of a field effect transistor is a significant barrier to heat conduction away from the channel and junctions at or adjacent the source/drain regions.
Accordingly, increase of temperature due to resistive losses in a channel of an FET causes increase of current in the channel or a portion thereof and further increases resistive losses with attendant temperature increase. If heat is not conducted away from the conduction region in sufficient degree to stabilize the semiconductor temperature, a phenomenon known as thermal runaway may occur, rendering the transistor inoperative for switching functions and often destroying the transistor structure.
To achieve highest densities of integration, FETs are often carefully scaled in channel width in consideration of anticipated current carrying requirements. For example, a transistor used to precharge a dynamic circuit prior to an input signal evaluation may be very narrow since the current drive requirements are very low. On the other hand, clocks, I/O circuits, off-chip drivers and logic circuits with large fan-out and the like, including electrostatic discharge (ESD) circuits must provide substantial current to a load and must have wide channels in order to do so. In addition, complementary MOSFETS are often used and the channel widths proportioned relative to the conduction properties of the channel corresponding to different impurity types and concentration, usually by a small multiple (e.g. three).
In practice, the channel widths of FETs engender marked irregularities in conduction properties. While the semiconductor material of which the channel is formed is a relatively good conductor of heat, under operating conditions approaching the performance limits of FETs of any known design, the conduction channel and source/drain regions may develop substantial thermal gradients from the center to the edges thereof, transverse to the conduction path. Specifically, if a transistor is assumed to be of a constant initial temperature throughout its structure, the conduction would ideally be constant across the channel. Resistive losses should also initially be constant across the channel.
However, while heat generated from the resistive losses can be removed from the edges of the channel, heat generated near the center of the channel must be largely conducted laterally to the edges of the channel. Since heat conduction depends on the thermal gradient, heat cannot be conducted away from the center of the channel until a thermal gradient develops. The existence of a thermal gradient from the center to the edges of the channel, when developed, implies stronger conduction at the center of the channel with attendant additional resistive losses near the center of the channel. Therefore, the temperature and current near the center of the channel may become much larger than at the edges and, unless sufficient heat can be conducted through the channel to its edges and then away from the transistor to stabilize the thermal gradient and maximum temperature, thermal runaway and destruction of the transistor may result.
Accordingly, thermal dissipation properties of the transistor may be the principal limitation on transistor performance and operating conditions. Unfortunately, at high integration density and small device sizes, particularly when integrated circuit designs include isolation structures, the individual active devices have very small thermal mass while heat removal from the FET channel regions may be limited. Therefore, large thermal gradients may develop in individual FETs over a relatively few switching cycles (performed at increased clock rates enabled by increased integration density) which may vary radically between individual transistors while heat removal designs can operate only at a much larger scale and accommodating the average heat dissipation of a relatively large number of transistors.
Further, it should be recognized that integration density is generally limited by lithographic resolution at any given minimum feature size regime. Therefore, any structure of minimum feature size or larger directed to controlling thermal conditions or "ballasting" to balance voltage and current conditions within an individual transistor implies a relatively large transistor size and compromise or limitation of integration density that could otherwise be achieved. To date, no structure has been proposed which does not impose a trade-off between these conflicting goals. That is, in summary, circuit performance. functionality and manufacturing economy goals may impose limitations on performance of individual transistors which, in turn, impose limitations of the circuit performance goal which may be achieved while worst case transistor operating conditions may limit the realization of integrated circuit performance and reliability criteria which could otherwise be achieved at any given minimum lithographic feature size regime.
Additionally, it is known to form source or drain contacts to transistors by selectively depositing a layer of metal on corresponding semiconductor material regions and heat treating the substrate to alloy the metal and semiconductor and form a "salicide" (self-aligned silicide). A salicide may also be deposited directly and further alloyed with semiconductor material. It is also known that salicide preferentially develops (or is deposited) in a relatively high resistance phase state referred to as C49 that, when contacts are formed, must be converted into a low resistance phase state known as C54.
It has also been recognized (but maintained as confidential proprietary information and not published) that the C49 phase state of salicide becomes increasingly difficult to convert to the C54 phase state of salicide as the dimensions of the salicide film are reduced. While not wishing to be held to any particular theory underlying this phenomenon, it appears that nucleation site density for conversion from C49 to C54 salicide diminishes greatly at a critical dimension between 0.9 and 0.6 micrometers (or areas of about 35 and 28 square micrometers, respectively) although the difficulty of conversion can be observed over a somewhat larger range. For example, nucleation site density has been observed to diminish by one-half over a dimensional range of 3.0 to 0.6 micrometers (the former corresponding to an area of about 88 square micrometers) causing diminution of successful conversion from 76% to 19.6% over that range of dimensions.
This effect has effectively imposed a minimum contact size on the design of FETs which must carry significant current where the additional resistance could not be tolerated (but not necessarily on the design of low current devices such as pre-charge transistors alluded to above). The contact size limitation, however, has not been significant at lower integration densities than are currently being developed. Further, no exploitation of this effect to achieve meritorious or beneficial electrical characteristics or any other semiconductor device design advantage or attribute has been proposed.